The present invention relates to integrated circuit devices and, more particularly, to integrated circuit driver devices and charge pumps.
Phase-locked loop (PLL) circuits are frequently used to generate highly accurate internal clock signals on an integrated circuit substrate. Typical PLL circuits include charge pumps that selectively source current to and sink current from a loop filter which controls an oscillator stage of the PLL circuit. This oscillator stage may be a voltage-controlled oscillator (VCO) stage. The amount of charge (Q) provided by the sourcing or sinking currents may be proportional to the duration of an active period of a control signal provided to the charge pump.
One example of a conventional charge pump that may be used in a PLL circuit is described in U.S. Pat. No. 6,124,741 to Arcus. In particular, FIGS. 3-6 and 9 of the ""741 patent illustrate various charge pumps that include current sources defined by a plurality of MOS transistors. These MOS transistor are arranged as a totem pole of upper PMOS and lower NMOS transistors that are connected in series (source-to-drain) between a power supply line (Vdd) and a ground reference line (Vss).
Control circuitry is also provided to drive the MOS transistors in a manner that matches the up/down current pumping by reducing Vds variations. PLL circuits are also described in U.S. Pat. No. 6,222,895 to Larsson and in published U.S. application Ser. No. 2001/0052806 A1 to Gu et al. U.S. Pat. No. 6,388,499 to Tien et al., assigned to the present assignee, also discloses a totem pole arrangement of MOS transistors that can be used in a signal driver.
Integrated circuit charge pumps according to embodiments of the present invention reduce parasitic charge injection from signals that drive control inputs of the charge pumps. This reduction in parasitic charge injection can be utilized to lower phase error when the charge pumps are used in phase-locked loops (PLLs). In some embodiments, an integrated circuit charge pump includes an output current source and a control circuit that drives the output current source with control signals in a preferred manner. The output current source may include a totem pole driver therein. This totem pole driver includes at least an upper PMOS supply transistor and a lower PMOS current source transistor that are disposed in series in a pull-up path extending between an output of the driver and a power supply line (e.g., Vdd). The totem pole driver also includes at least an upper NMOS current source transistor and a lower NMOS supply transistor. These NMOS transistors are disposed in series in a pull-down path extending between the output of the device and a reference line (e.g., Vss). The control circuit may include a pull-up control circuit and a pull-down control circuit. The pull-up control circuit is configured to drive a gate of the upper PMOS supply transistor with a PMOS turn-on voltage in response to a leading edge of a pull-up control signal. The pull-up control circuit is further configured to simultaneously drive a gate of the upper PMOS supply transistor with a PMOS turn-off voltage and a source of the lower PMOS current source transistor with a first non-zero turn-off reference voltage (e.g., PVT), in response to a trailing edge of the pull-up control signal.
In some additional embodiments, the pull-up control circuit includes a first output that is electrically coupled to the gate of the upper PMOS supply transistor and a second output that is electrically coupled to a source of the lower PMOS current source transistor. This second output of the pull-up control circuit is preferably disposed in a high-impedance state in response to the leading edge of the pull-up control signal. In the event the pull-up path includes only two PMOS transistors, then the second output of the pull-up control circuit may be electrically coupled to a source of the lower PMOS current source transistor and a drain of the upper PMOS supply transistor. A gate of the lower PMOS current source transistor may also be held at a first bias voltage (e.g., VP1).
The pull-down control circuit is preferably configured to drive a gate of the lower NMOS supply transistor with an NMOS turn-on voltage in response to a leading edge of a pull-down control signal. The pull-down control circuit is further configured to simultaneously drive a gate of the lower NMOS supply transistor with an NMOS turn-off voltage and a source of the upper NMOS current source transistor with a second turn-off reference voltage (e.g., NVT less than Vdd) in response to a trailing edge of the pull-down control signal. Moreover, the pull-down control circuit may include a first output that is electrically coupled to the gate of the lower NMOS supply transistor and a second output that is electrically coupled to a source of the upper NMOS current source transistor. This second output of the pull-down control circuit is preferably disposed in a high-impedance state in response to the leading edge of the pull-down control signal. In the event the pull-down path includes only two NMOS transistors, then the second output may also be electrically coupled to a drain of the lower NMOS supply transistor. A gate of the upper NMOS current source transistor may also be held at a second bias voltage (e.g., VN1).
According to preferred aspects of these embodiments of the present invention, the pull-up control circuit includes a PMOS access transistor. This PMOS access transistor has a first current carrying terminal (e.g., source) that is electrically coupled to the source of the lower PMOS current source transistor and a second current carrying terminal (e.g., drain) that is held at the first turn-off reference voltage. The PMOS access transistor is preferably sized to match the upper PMOS supply transistor in width and length, to reduce switching noise and charge injection caused by capacitive coupling in the pull-up path. The pull-down control circuit also includes an NMOS access transistor. This NMOS access transistor has a first current carrying terminal (e.g., drain) electrically coupled to the source of the upper NMOS current source transistor and a second current carrying terminal (e.g., source) that is held at the second turn-off reference voltage. The NMOS access transistor is preferably sized to match the lower NMOS supply transistor in width and length, to reduce switching noise and charge injection caused by capacitive coupling in the pull-down path.
According to still further preferred aspects of these embodiments, the pull-up control circuit is configured to include first and second delay-balanced inverter strings that drive the gate of the upper PMOS supply transistor and a gate of the PMOS access transistor, respectively, in response to the pull-up control signal. These delay-balanced inverter strings may include an uneven number of inverters, with one or more delay elements providing an equivalent inverter delay. The pull-down control circuit is also configured to include a pair of delay-balanced inverter strings that drive the gate of the lower NMOS supply transistor and a gate of the NMOS access transistor in response to the pull-down control signal.